The present invention relates to decoding instructions in a computer system such as a processor.
In a computer system, instructions are typically fetched from a program memory, decoded and supplied to an execution unit where they are executed to run the program stored in the program memory. It is advantageous for such a computer system to be able to support more than one instruction mode. A novel computer system described herein can support three instruction modes.
According to a first instruction mode, during each machine cycle two 32 bit instructions are decoded, referred to herein as GP32 mode.
According to a second instruction mode, during each machine cycle a pair of 16 bit instructions are decoded, referred to herein as GP16 mode.
According to a third instruction mode, four 32 bit instructions are decoded during each machine cycle, referred to herein as VLIW mode.
In practice, a prefetch unit fetches a word from memory having a length of 128 bits. This word can contain eight 16 bit instructions (GP16 mode), four independent 32 bit instructions (GP32) or four interrelated 32 bit instructions (VLIW mode). The four 32 bit instructions in VLIW mode are interrelated in the sense that they have to conform to a certain grammar such that they can be fetched and supplied to the decoder together. The prefetch unit supplies an 128 bit sequence to the decode unit on each machine cycle. However, the decode units should supply to the execution unit decoded outputs only for the instructions to be decoded in that machine cycle, which depends on the instruction mode.
In the second instruction mode, the nature of the 16 bit instructions can sometimes limit the manipulations to be carried out by the execution unit. It is therefore advantageous to allow a 32 bit instruction to be included in a sequence of instructions in GP16 mode. If this is done however then it would be necessary to include an instruction to alter the instruction mode of the computer system each time prior to execution of a 32 bit instruction and then to have an additional instruction to change the mode back again to continue to decode and execute 16 bit instructions.
According to the present invention in one aspect there is provided a decode unit for decoding instructions in a processor including instructions of a first length in a first instruction mode and instructions of a second, shorter length in a second instruction mode, the decode unit including: decoding circuitry for decoding instructions; a register for holding the instruction mode and generating an instruction mode signal; switching circuitry responsive to the instruction mode signal to output decoded instructions from the decode unit depending on the instruction mode; and means for detecting a length change instruction of the second, shorter length while in the second instruction mode which indicates that the subsequent instruction is of the first length and for temporarily altering the state of the instruction mode signal to allow the first length instructions to be decoded without changing the instruction mode held in the register.
In another aspect the present invention provides a processor comprising: at least one execution unit for executing instructions; an instruction mode indicator which indicates one of a plurality of instruction modes for the processor; a decode unit for decoding instructions prior to dispatch to the at least one execution unit; and an instruction supply mechanism for supplying instructions to the decode unit, wherein said instructions are represented by bit sequences the length of which depends on an instruction mode of the processor, and wherein the decode unit comprises: decoding circuitry for decoding the instruction; switching circuitry responsive to an instruction mode signal generated by the instruction mode indicator to output decoded instructions from the decode unit depending on the instruction mode; means for detecting a length change instruction of a second length while in a second instruction mode which indicates that the subsequent instruction is of a first length and for temporarily altering the state of the instruction mode signal to allow the first length instruction to be decoded without changing the instruction mode held at the instruction mode indicator.
In a further aspect, the invention provides a method of decoding instructions in a processor, the instructions each being of a predetermined length and including a length change instruction which indicates that a subsequent instruction is of a different length, the method comprising: detecting the length change instruction in a decode unit; temporarily altering the outputs of the decode unit to permit the different length instruction to be decoded; and after the different length instruction has been decoded, defaulting to decoding of the instructions of the predetermined length.
The length change instruction is named herein as Gp32nxt. It thus allows a 32 bit instruction to be decoded and executed while the machine remains in GP16 mode. This gives GP16 mode a greater flexibility than it would have if all instructions were restricted to the 16 bit length. Moreover, it overcomes the need to change the mode of the computer system just to execute a single 32 bit instruction in an instruction sequence of 16 bit instructions.
It will be appreciated that the length change instruction and the following 32 bit instruction needs to be atomic, i.e. executable without any interrupts. This is because once the decoder has detected the length change instruction, the next output from the decoder will be as though a 32 bit instruction has been decoded. The decode circuitry comprises in the preferred embodiment a first decoder having an input connected to receive a bit sequence of the first length and operating on receipt of said bit sequence to generate a first decoded output; a second decoder having an input connected to receive a bit sequence of the second length and operating on receipt of said bit sequence to generate a second decoded output; and a communication path for supplying a bit sequence simultaneously to said first and second decoders.
Thus, as described in the following, in order to manage different instruction modes, the decode unit has a plurality of dedicated decoders each of which receives and decodes the bit sequence during each machine cycle. Depending on the instruction mode of the machine, the outputs of selected one of the decoders are supplied to the execution unit for execution. The outputs of the other decoder are not required and thus are not selected.